1. Field of the Invention
The present invention relates to an integrated circuit embedded with single-poly non-volatile memory (NVM) fabricated using an application specific integrated circuit (ASIC) or conventional logic process.
2. Description of the Prior Art
In previous designs, an electronic system would be based on a board populated with a microprocessor or micro-controller, memory, discrete peripherals, and a bus controller. Today, such a system can fit on a single chip, hence the term System On Chip (SOC). SOC is an IC consisting of a processor, embedded memory, various peripherals, and an external bus interface. Embedded memory can be either volatile (SRAM, DRAM) or non-volatile (ROM, Flash). Peripherals vary from the general purpose (Counter/Timers, UART, Parallel I/O, Interrupt controller, etc) to the specialized (LCD Controller, Graphics Controller, Network Controllers, etc). The external bus interface allows the SOC to interface with external memory devices and peripherals with little or no glue logic. Almost every semiconductor company that has a processor, or access to one, is developing SOC products. This advancement in technology allows system designers to reduce system testing and size, improve reliability, and shorten the time to market for their products.
It is desirable, when embedding memory cells into a standard logic process, to do so without changing the single-poly process typically used in the fabrication of the logic circuitry. This desire has led to the development of a single-poly ROM cell having N+ source and N+ drain regions formed in a P− substrate and a polysilicon gate overlying a channel region extending between the source and the drain. An N diffusion region formed in the P− substrate serves as the control gate and is capacitively coupled to the floating gate via a thin oxide layer. The oxide layer has a tunnel window opened in a portion thereof near the N+ drain to facilitate electron tunneling. The control gate and floating gate of this single-poly ROM cell form a capacitor in a manner similar to that of the more traditional stacked-gate, or double-poly, EEPROM cells. However, the above-described N-channel single-poly ROM cell is disadvantageous since it requires programming and erasing voltages of 20 V. These high programming and erase voltages limit the extent to which the size of such cells may be reduced.
Sung and Wu, in U.S. Pat. No. 6,044,018, disclose a single-poly memory device that can be fabricated with a conventional CMOS process sequence. A complimentary cell couples the floating gate of an NMOS device to the floating gate of a PMOS device. Each gate at least partially overlaps a source region and a drain region. A channel-stop region adjacent to the source of the PMOS device inhibits formation of a channel between the source and drain, and hence essentially eliminates current flow from the drain to the source in the PMOS device, even when a voltage is present between the source and drain and the floating gate has sufficient potential to otherwise initiate a channel.
Nevertheless, the single-poly memory device disclosed in U.S. Pat. No. 6,044,018 suffers from several drawbacks. First, the prior art memory device consumes a lot of chip area since it is composed of a PMOS device and an NMOS device, and hence an extra field oxide layer is needed for isolating the PMOS form the NMOS. Second, the prior art EEPROM cell needs an extra channel stop region and the formation of a conductor for connecting two gates, this, in turns, means extra process steps and thus raised cost.